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Creating Subcircuits in Multisim

In the previous article we analyze how the multi-page design can help us have a better organization of our circuit. Following the philosophy of "divide and conquer" continue studying the design blocks in Multisim, and this time we will learn to use subcircuits in our designs.

A subcircuit is a circuit in Multisim to reduce to a single block for a better organization of our schematic. Towards a programming analogy, a subcircuit is equivalent to a subroutine. Here is an example.

The following is an excerpt from a counter circuit:

As you can see, we have a clock generardor based on the 555 (enclosed in box) that connects to terminal 14 (CLK) of 74190N, here is more detail the clock signal generator :

To simplify our design in Multisim, we will convert the signal generator subcircuit clock, so be represented as a single block in the schematic. To do this first we select all the components that make up the clock signal generator:

Now select the menu Place>> Replace Subcircuit. Enter a name for the subcircuit:

We click OK and place the subcircuit on the workspace:

Ready, we have reduced generator clock signal to a single block: a subcircuit. In the window Design Tools can see the hierarchy of our design. We have the main circuit ( Counter ) and subcircuit clock. Note that the latter has an icon with an S, this indicates a subcircuit.

If necessary to view and / or modify the subcircuit, simply select the window Design Tools in Multisim to open it:

The subcircuits in Multisim are saved along with the main file so if you move the main file to another location, it automatically moves the subcircuit. The disadvantage is that the file size can be large, clear, depending on the complexity of design. Another aspect to consider is that a subcircuit can not be reused in other designs of Multisim. For this blocks are hierarchical, they talk in a later entry.

As always welcome comments and questions.

Greetings! Fernando

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Creating a Multi-page Design

As the complexity and size of an electronic design grows it becomes more necessary to have a better organized. We must always bear in mind that our diagram should be clear, easy to modify, and easy to read by others. To help with this challenge Multisim Design offers blocks, they are still the philosophy of "divide and conquer." The main idea is to split a large diagram in small plots easy to manage and update. There are three options in the Multisim design blocks, subcircuits, hierarchical blocks, and mult-ipágina design. In this last talk today.

As mentioned earlier, the idea of \u200b\u200bmulti-page design is to divide a large design and confused individual pages interconnected. As illustrated in the following figures, instead of having one large sheet, we can have our design on individual sheets:

To connect our circuit from one page to another using the off-page connectors , which are Multisim menu Place >> Connectors :

Here's how to make a multi-page design with a simple design. We will refer to the following circuit:

Let's split the previous circuit into two sections, A and B. The division was made at nodes 3 and 0:

Now let's add one more page to our design, and the page will post the section B. For this select Place >> Multi- page. Multisim will ask the name of this page, this case the name 2. Multisim will create a new page with the same status as the first. This can be corroborated in the window Design Tools:

leaf can change in just to click on them.

As next step go to page 1, select it and cut the circuit section B and paste it on page 2, so that now we have the Section A of the circuit on page Filter # 1 and Section B in Filter # 2 . To connect the two pages (and of course both nodes) we will use off-page connectors. Place selected >> Connectors>> Connector Outside P OAR. Place two of these connectors in the workplace:

Open the properties of the first connector (FueraPágina 1) and rename it to 3 (the node of interest.) Do the same with the connector FueraPágina 2, but in this case rename it to 0. Then connect the connectors to the respective owner nodes:

A hour we sheet Filter # 2 and repeat the same operation. Multisim will alert us that connectors with the same nodes ( 0 and 3) already exist, we will accept this change to connect 'virtual' between the two p OAR Circuit:

Ready! We now have a multi-page design. Off-page connectors virtual connections (or wireless) between the different sheets. We simulate the circuit and transfer to Ultiboard Multisim seamlessly as is our design as one.

Some notes before the end:

1. multi-page design is recommended when we have circuits that tend to be flat / horizontal.
2. All sheets of the circuit multi-page design are stored in one file.
3. saved file size tends to be large because it contains several pages.
4. can not reuse pages from a multi-page design in other circuits.

As always questions and comments are welcome.

soon,

Fernando

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LAVA TRAIL: mission accomplished Photos: Alberto R. Cardona

With nearly three hundred participants were given the outputs in the different modalities of this groundbreaking trial on the island of volcanoes. With the moon setting in Famara and the first light of dawning sun by Arrieta began early risers. After the departure from the sandy beach of La Garita and just over a mile and a half, began the climb towards the crags of Chache (highest point of the island of Lanzarote), from there you descend through a very technical trail to the sand on one beach, Playa de Famara, this time on the opposite coast. Before reaching the first supplies (PK35), the rate marked on the front of the stage coupled with uneven and technical terrain saved the descent, had no second thought and went on to take its toll by making walking a few participants. The course designed by the organization (Vulcano Triathlon Club) ran through the beautiful landscapes of Lanzarote (incredible beaches, gorges unknown volcanoes and lava, green-tinged mountains ,...) to the astonishment of many, both foreign and local unaware of others beyond the volcanic landscapes of the island hutch. WHITE BEACH TEJEDA A: Sergio Espinosa (8:57:08) he crossed the finish line after the Gran Canaria (De Tejeda to be exact) Gregorio Armas (8:32:58), winner of this first edition of the LAVATRAIL. The first woman would be Teresa Hernández Barrera (11:09:20). CESAR JAVIER : DORSAL 0 The goal was, next to her tenacious mother, Cesar Javier, conejero child with Lesch-Nyhan syndrome (severe disease), which together with the race organizers were trying to raise funds for the acquisition a car adapted to your needs (grants: 2052 8029 25 3310394508).

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LANZAROTE LAVA TRAIL: 19 FEBRUARY 2011

On Saturday February 19 will bring the first "ultra" mountain of the island of Lanzarote. With multiple modes (extreme, marathon, starter, equipment) for all levels, emphasize the queen away with 82 miles to go from the beach of La Garita, in the town of Haria in the north of the island to Playa Blanca the south. Arista Component Team Off Road Team, Sergio Espinosa, will be in the starting line, mixed with all participants to start running at 7:00 to follow the path chosen by the organization. More informacón in Www.lanzarotedeportes.es

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Building Code Multisim VHDL from Multisim - Part 2 Creating

from Multisim VHDL Building Code - Part 1

Continuing with the tutorial create VHDL code from a Multisim schematic in the first half we created a new design in Multisim PLD where we define the input and output logic circuit. Now let us capture the diagram, remember that our goal is function X = AB + CD , where A, B, C and D will tickets switches (SW0, SW1, SW2, SW3) and X is an LED (LED0 .)

Select the menu Place>> Component ... to open the browser components. It is noteworthy that since we are in LDP mode, the master database est to find only limited and related components digital logic. Take a moment to explore different groups and families are available in the Multisim database.

Now let PLD Logic Group , Family LOGIC_GATES and select the component AND2 (we will need two AND gates), also require an OR. Connect the circuit as shown in the figure below:

In summary remember q SW0 to SW3 entries correspond to real switches, and output to an indicator LED0 the logical function would be embedded in the FPGA chip. Here's part of the truth table for this circuit:

X = AB + CD

A	B	C	D	AB	CD	X
0	0	0	0	0	0	0
0	0	0	1	0	0	0
0	0	1	0	0	0	0
0	0	1	1	0	1	1

To test we simply plug our circuit input and an output indicator, or we can create another test circuit which is (we'll leave for another article), for the moment let's focus on the VHDL code generation. For this in Multisim go to menu Transfer >> Export to PLD ...

In the previous window we see that there are several options, assuming you have not connected any FPGA chip card we only generate the VHDL. We click Next , select a route for save the file, click Finish and ready. Multisim creates two files with the vhd. These files can be opened with a text editor. Here is a part:

In summary we conclude that the new PLD Multisim schematic can create a logic circuit and generate the VHDL code (required to program a FPGA) automatically. On the other hand, the PLD module works fine with the card NI Digital Electronics FPGA Board of National Instruments, which is ideal for laboratory acetic pr. In this card you can download VHDL code directly from Multisim.

I hope you have enjoyed this introduction to PLD schematic, do not forget to send your questions and comments.

soon,

Fernando

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2 Stage Off Road Race MTB Rogaine Board The wild

29 and January 30, organized by La Santa Sport, was held on the island of Lanzarote 4th MTB Off Road Race. Moved to the island several components of the Off Ridge Road, (Sergio Jover, Sergio Espinosa, Fernando González and Ferko) and Arista club; (Elena Marrero) both to participate and to follow the race, achieving complete all the two-day BTT, performing on Saturday, a journey of 34km and 60km on Sunday. Some pictures of the test:

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The team preparing for departure.

Yaiza and Elena before departure.

Ferko at Timanfaya.

All info on the following link: http://www.clublasanta.es/2-stage% 20Off-Road% 20MTB% 20Tour% \u200b\u200b20Race-10742.aspx

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2011. The cooler day. The Wild Boar Rogaine

-4C °, only to write and give cold temperature that is endured by the team members and O-Rientate Arista in the Wild Rogaine Board 2011.

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from Multisim VHDL Code - Part 1

Creating VHDL code from Multisim - Part 2

Design address is changing and one trend is to use embedded devices such as FPGA . These devices internally contain millions of gates reconfigurable programmable logic. We can take a logical function, eg X = AB + CD , and download the FPGA chip, the FPGA internally 'burn' the routes needed to create such a function ng. The main advantage of this lies in the fact that the logic function is hardware, which offers greater reliability in a system.

to program FPGAs using a hardware description language or HDL, the most by using VHDL. This language is text based so it is necessary to know the syntax of it. To learn more VHDL code I recommend a tutorial blog to Help Electronics only gives click here.

In Multisim 11 (and later) versions Student Educational and there is a new feature called Schematic PLD (Programmable Logic Device), and the idea is to create a logic circuit using gates, flip flops, buffers, etc.. and then automatically create the VHDL code necessary to program a FPGA chip. This save much design time.

I note that the PLD of Multisim Schematic was designed in such a way that works hand in hand with a card from National Instruments called Digital Electronics NI FPGA Board . This card is great for pr acetic digital electronics and chip contains a Xilinx Spartan-3E FPGA, as well as peripherals such as LEDs, switches, etc. This card connects via USB to the PC and once generated VHDL code Multisim is ready we can download the FPGA chip on the card.

other chips can be programmed FPGA that are 32 bits and supported by the Xilinx ISE software, this requires a little more work. If you are interested let me know to refer to more resources.

An example of the use of PLD in Multisim Schematic. Our goal will be to perform the function X = AB + CD , so we need four inputs (A, B, C and D) and output (X), as shown in Figure following:

Multisim We will open and select File >> New >> PLD Design ...

Multisim In this first step asks us if we will use the digital card that I mentioned earlier, a new configuration file, or just an empty project. I will select the first option and click the Next :

The name of my design is Logic Function and the FPGA chip used by the digital card is NI XC3S500E. We click Next :

In the previous window we can see the list of input / outputs available on the digital card from NI. I'll select the switches SW0 , SW1, SW2 and SW3 entries corresponding to A , B , C and D my logic function, and for output X will use the LED0 . We

click Finish , Multisim create a blank layout and placement of inputs and outputs selected in the workspace:

The following is to capture our logic circuit, but we'll leave for the next part of the tutorial.

Stay tuned and do not forget to add you to the list of supporters of the blog, so will you updates.

Greetings!

Fernando

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